The present invention relates to a thin layer forming method and a semiconductor device producing method, and more particularly to a thin layer forming method and a semiconductor device producing method by each of which a flattened insulating layer or the like can be formed in a VLSI producing process or the like.
In a semiconductor device producing method, there has been recently required, for high integration and miniaturization of VLSIs, a technique of forming a flat insulating layer under a low-temperature condition.
The following description will discuss a conventional thin layer forming method and a conventional semiconductor device producing method with reference to attached drawings.
FIG. 13 (a) to (f) are section views illustrating the respective steps of a conventional method of producing a semiconductor device by which a flattened interlaminar insulating layer is formed on polysilicon electrodes serving as lower electrodes formed on a semiconductor substrate and an upper wiring pattern is formed on the interlaminar insulating layer.
As shown in FIG. 13 (a), gate electrodes 3 comprising polysilicon are formed on a semiconductor substrate 1 through gate oxide layers 2. On the semiconductor substrate 1, there are formed the sources and drains of MOS transistors, LOCOS oxide layers and the like, which are not shown for convenience sake.
As shown in FIG. 13 (b), formed on the semiconductor substrate 1 and the gate electrodes 3 is a silicate glass layer 4 serving as a flattened insulating layer containing boron and phosphorus (hereinafter referred to as BPSG layer) by a normal-pressure CVD method, the BPSG layer 4 being deposited in a thickness of 700 nm. In FIG. 13 (b), precipitates 5 are generated on the surface of the BPSG layer 4.
As shown in FIG. 13 (c), the BPSG layer 4 is thermally treated to soften the glass therein, causing the BPSG layer 4 to be flowingly flattened. As shown in FIG. 13 (d), first photoresists 6A having a desired resist pattern are formed on the BPSG layer 4, which is then etched.
As shown in FIG. 13 (e), after the first photoresists 6A have been removed, a metallic layer 7 of an aluminium-based alloy serving as an upper electrode is formed on the BPSG layer 4 by a sputtering method. Second photoresists 6B corresponding to a wiring pattern are formed on the metallic layer 7. As shown in FIG. 13 (f), the metallic layer 7 is etched. Thereafter, the second photoresists 6B are removed to form a wiring pattern 7' of the metallic layer.
As the method of flattening the BPSG layer, i.e., as the thermal treating method of softening glass (hereinafter referred to glass flow planarization), there are generally known two examples, in one of which the glass flow planarization is conducted in a nitrogen atmosphere and in the other of which the glass flow planarization is conducted in an oxygen/hydrogen atmosphere (hereinafter referred to as pyrogenic atmosphere).
According to a normal method in which glass flow planarization is conducted in a nitrogen atmosphere, a BPSG layer containing impurities such as boron, phosphorus and the like in prevailing concentrations, requires a heating treatment at a temperature in the vicinity of 900.degree. C. for thirty minutes. In a highly integrated element such as a 64-MDRAM or the like, however, diffusion zones for the sources and drains of MOS transistors are small. Accordingly, when a high-temperature heating treatment as above-mentioned is conducted, the profiles of impurities in the diffusion zones are changed. This makes it difficult to achieve a highly integrated element such as a 64-MDRAM.
It is therefore required to conduct the glass flow planarization at a lower temperature. As a method of conducting the glass flow planarization under 900.degree. C., e.g., 850.degree. C., it is considered to conduct the glass flow planarization in a pyrogenic atmosphere, instead of a nitrogen atmosphere.
As shown in FIG. 14, there occurs, in glass flow planarization in a pyrogenic atmosphere, a phenomenon that metallic electrodes and gate electrodes below a BPSG layer, and the transistor diffusion zones are oxidized. Accordingly, the polysilicon gate electrodes and the metallic electrodes are reduced in thickness. This increases the resistance or decreases the diffusion zones. Therefore, it is disadvantageously difficult to use glass flow planarization in a pyrogenic atmosphere.
In glass flow planarization to be conducted in a nitrogen atmosphere, it is considered to set, to high levels, the concentrations of impurities such as boron, phosphorus and the like, causing the temperature of heating treatment to be lowered.
With a scanning electron microscope, the inventors observed those portions of the BPSG layer 4 on the broad and flat semiconductor substrate 1 that had a thickness identical with that of each of the gate electrodes 3 after the glass flow planarization shown in FIG. 13 (c) had been conducted. Then, the inventors measured a flattened angle .theta. serving as an index which represented a flatness obtained by the glass flow planarization (See FIG. 15). At this time, the BPSG layer had a thickness of 400 nm.
FIG. 16 shows the results of a test in which, with the impurity concentration of each BPSG layer variously changed, glass flow planarization was conducted in a nitrogen atmosphere at each of temperatures of 850.degree. C. and 900.degree. C. for 30 minutes, and the flattened angles .theta. were measured. As apparent from FIG. 16, the BPSG layers were flattened more satisfactorily as the impurity concentration was increased. As to the temperature of glass flow planarization, the BPSG layer 4 was flattened more satisfactorily at 900.degree. C. than at 850.degree. C. In a highly integrated LSI, metallic wirings formed on a BPSG layer are fine. Accordingly, there is required an angle of not more than 25.degree. as the flattened angle .theta. for preventing the metallic wirings from being disconnected or short-circuited. Thus, as apparent from FIG. 16, there are required an impurity concentration of not less than 14 mol % for glass flow planarization at 900.degree. C., and an impurity concentration of not less than 19 mol % for glass flow planarization at 850.degree. C.
However, a BPSG layer containing impurities in high concentration presents the problem that the impurities therein absorb moisture in the air after the BPSG layer has been formed, so that precipitates are generated with the impurities serving as cores. FIG. 17 shows the relation between the time during which the BPSG layer has been preserved in the air, and precipitates generated from impurities in terms of the number of particles. FIG. 17 shows the results of a test in which BPSG layers having different impurity concentrations and each having a thickness of 400 nm, were respectively deposited on mirror-like silicon substrates and in which, with the use of a particle detecting device for conducting a reflection measurement by scanning laser light on the surfaces of the BPSG layers, the precipitates were measured for numbers at several times for hundreds hours immediately after the deposition of the BPSG layers. As apparent from FIG. 17, there was observed an increase in the number of precipitates in a very short period of time with an increase in impurity concentration, and the precipitates were remarkably generated for an impurity concentration of about 19 mol % or more. Even though the concentrations of boron and phosphorus are low, such precipitates are generated since boron and phosphorus absorb a great amount of moisture.
Since such precipitates remain after the BPSG layer has been flattened, the metallic wirings formed on the BPSG layer are disconnected or short-circuited. This disadvantageously makes it difficult to achieve a highly integrated transistor.